1. Field of Invention
The present invention relates to a method of fabricating integrated circuits. More particularly, the present invention relates to a method of fabricating small dimension wires in integrated circuits.
2. Description of Related Art
With steadily increasing integration in integrated circuit (IC) fabrication, the dimensions of IC devices are greatly reduced. Accordingly, in a process of fabricating dynamic random access memory (DRAM), the areas of a metal oxide semiconductor (MOS) have to be made very small. However, due to limitations imposed by the resolution of the photolithographic process, bit lines cannot be fabricated with a very narrow width. Thus, in the following process, there is not much space for node contact windows and the alignment has to be very accurate.
Conventional method of fabricating bit lines is sequentially forming a silicon oxide layer, a doped polysilicon layer, and a tungsten silicide layer on the substrate. Then a photoresist layer is coated on the tungsten silicide layer. After the process of exposure and development, part of the photoresist layer with a bit line pattern is formed.
The bit lines are defined by using the bit line pattern of the photoresist layer as a mask to etch the tungsten silicide layer and the doped polysilicon layer by an anisotropic etching process, thus defining the bit lines. The photoresist layer is removed, while the bit lines including the tungsten silicidetungsten silicide layer and doped polysilicon layer are remained.
Openings lie between the bit lines, and the width of openings is the largest dimension that the node contact windows can be formed in the subsequent processes. Narrower bit lines would allow wider openings, which in turn would allow a higher tolerance for node contact window accuracy. A higher tolerance would significantly reduces the difficulty of the process.
It can be seen that conventional processes are not able to meet the demands of current technology. For example, in a 0.21 .mu.m DRAM, it is necessary to fabricate lines with dimensions less than 0.15 .mu.m. At present, this requires a better stepper in the photolithography process.